Method of manufacturing semiconductor device

ABSTRACT

A method of manufacturing semiconductor devices, including the steps of forming an insulating layer on a semiconductor substrate in which predetermined structures are formed, and etching the insulating layer to expose a predetermined region of the semiconductor substrate, thereby forming a contact hole, forming an insulating layer on the sides of the contact hole, and forming a conductive layer within the contact hole, forming a contact plug. It is possible to prevent a short problem by sufficiently securing a distance between a drain contact plug and a virtual power line.

BACKGROUND OF THE INVENTION

The invention relates in general to a method of manufacturingsemiconductor devices and, more particularly, to a method ofmanufacturing a semiconductor device, wherein short problems can beprevented by sufficiently securing a distance between a drain contactplug and a virtual power (VIRPWR) line.

In general, the erase operation of a flash memory device is performed bydischarging the electrons of a floating gate from a semiconductorsubstrate by means of Fowler-Nordheim (F-N) tunneling. The eraseoperation is performed by applying a high voltage (about 20 V) to thesemiconductor substrate. The flash memory device includes a page bufferfor reading data stored in a memory cell array. The page buffer isconnected to the bit line of the memory cell array through a bit lineselection unit.

FIG. 1 is a circuit diagram showing the constriction of a bit lineselection unit.

Referring to FIG. 1, an even bit line select transistor HV1 and an oddbit line select transistor HV2 are serially connected between an evenbit line BLe and an odd bit line BLo in order to select either of theeven bit line BLe and the odd bit line BLo according to even and odd bitline bias signals DISCHe and DISCHo. Virtual power (VIRPWR) is appliedto the bit line through the transistors HV1 and HV2. Furthermore, thebit line selection unit includes a connection transistor HV3 forconnecting a connection node SO and the even bit line BLe and aconnection transistor HV4 for connecting the node SO and the odd bitline BLo. The connection transistor HV3 and the connection transistorHV4 are driven according to the even and odd bit line select signalsBSLe and BSLo, respectively. Each of the bit line select transistors HV1and HV2 and the connection transistors HV3 and HV4 includes a highvoltage NMOS transistor. The connection node SO is a connection node ofa bit line selection unit and a page buffer.

The bit line selection unit constructed as described above is connectedto the junction of the even bit line BLe and the select transistor HV1at a node Q1. The select transistor HV1 is driven in response to theeven bit line bias signal DISCHe, so that a ground voltage Vss or apower supply voltage Vcc applied through the virtual power (VIRPWR) lineis applied to the bit line. The bit line selection unit is alsoconnected to the junction of the odd bit line BLo and the selecttransistor HV2 at a node Q2. The select transistor HV2 is driven inresponse to the odd bit line bias signal DISCHo, so that the groundvoltage Vss or the power supply voltage Vcc supplied through the virtualpower (VIRPWR) line is applied to the bit line.

FIG. 2 is a cross-sectional view of a contact plug for connecting thejunction of a bit line of a bit line selection unit and a bit lineselect transistor, and a virtual power (VIRPWR) line.

Referring to FIG. 2, an insulating layer 22 is formed on a semiconductorsubstrate 21 in which predetermined structures are formed. A contactplug 23, which is connected to the junction (not shown) of a bit lineselect transistor, is formed at a predetermined region of the insulatinglayer 22. Furthermore, a bit line 24 and the contact plug 23 areinterconnected, and the contact plug 23 and a virtual power (VIRPWR)line 25 are spaced apart from each other at a predetermined distance. Inaddition, between-the bit line 24 and the virtual power line 25 keepsinsulated by means of an insulating layer 26.

In the bit line selection unit having the above-mentioned cross section,however, a distance between the contact plug 23 and the virtual powerline 25 that is varied according to the cell operation cannot be securedsufficiently. Accordingly, at the time of a cycling test, a leakage pathis formed, resulting in failure in the erase operation. This degradesthe reliability of the device.

SUMMARY OF THE INVENTION

Accordingly, the invention addresses the problems described above anddiscloses a method of manufacturing a semiconductor device, wherein ashort problem can be prevented in such a manner that a distance betweena drain contact plug and a virtual power line can be securedsufficiently by forming an insulating layer on the sides of a draincontact hole.

According to one aspect, the invention provides a method ofmanufacturing a semiconductor device including the steps of forming aninsulating layer over a semiconductor substrate, etching the insulatinglayer to expose the semiconductor substrate to form a contact holehaving sides, forming an insulating layer on the sides of the contacthole, forming a conductive layer within the contact hole to form acontact plug, recessing a portion of a top surface of the insulatinglayer, and etching a portion of upper portions of the conductive layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing the constriction of a prior art bitline selection unit;

FIG. 2 is a cross-sectional view of a prior art contact plug forconnecting the junction of a bit line of a bit line selection unit and abit line select transistor, and a virtual power (VIRPWR) line; and

FIGS. 3A to 3D are cross-sectional views illustrating a method ofmanufacturing a semiconductor device according to an embodiment of theinvention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Various embodiments of the invention will be described with reference tothe accompanying drawings. Because various embodiments are provided forthe purpose that the ordinary persons skilled in the art are able tounderstand the inventions, they may be modified in various manners andthe scope of the invention is not limited by the various embodimentsdescribed later.

FIGS. 3A to 3D are cross-sectional views illustrating a method ofmanufacturing a semiconductor device according to an embodiment of theinvention. FIG. 3 shows a method of forming a bit line selection unitfor connecting a bit line and a page buffer and a drain contact plug ofa high voltage transistor in a NAND flash memory device.

Referring to FIG. 3A, an insulating layer 102 is formed on asemiconductor substrate 100 in which predetermined structures includinga high voltage transistor are formed. The insulating layer 102 is etchedsuch that a predetermined region of the semiconductor substrate 100, forexample, the drain of the high voltage transistor is exposed, therebyforming a drain contact hole 104.

An insulating layer 106 is formed within the drain contact hole 104. Anetch-back process is then performed so that the insulating layer 106remains only on the sides of the drain contact hole 104. The insulatinglayer 106 may preferably be formed to a thickness of 30 Å to 100 Å andmay be formed using a nitride layer, preferably, Si₃N₄, by a chemicalvapor deposition (CVD) or atomic layer deposition (ALD) method, whichcan secure the wet etch selectivity with an oxide layer.

Referring to FIG. 3B, a conductive layer 108 is formed on the entiresurface in such a way to bury the drain contact hole 104. The conductivelayer 108 may preferably be formed of polysilicon. The conductive layer108 is polished until a top surface of the insulating layer 102 isexposed, forming a drain contact plug 110 including the insulating layer106 and the conductive layer 108.

Referring to FIG. 3C, a wet etch process is performed to partiallyrecess a top surface of the insulating layer 106. In the wet etchprocess, a H₃PO₄ solution is preferably used and the insulating layer106 is removed preferably to a thickness of about 50 Å to 100 Å.

Referring to FIG. 3D, a dry etch process is then performed to makerounded (a) top corners of the conductive layer 108. The dry etchprocess may preferably be carried out using a microwave equipment inwhich it allows for an isotropic etch process and a bias is not appliedto the cathode electrode or an equipment in which a inductively coupledplasma (ICP) type source is mounted, for example.

Furthermore, at the time of the dry etch process, a mixed gas of SF₆ andCl₂, which facilitates isotropic etch, is preferably used. If it isnecessary to control the etch selectivity with the insulating layer, anoxygen (O₂) gas may added to the mixed gas of SF₆ and Cl₂. In this case,an amount of the O₂ gas in the mixed gas of SF₆ and Cl₂ is preferablyabout 5% to 10% of the total amount of the mixed gas of SF₆ and Cl₂.Alternatively, an etch process using hot SC-1 solution may be performedinstead of the dry etch process. In this case, the conductive layer 108is etched to a thickness of about 100 Å to 300 Å through the etchprocess.

As described above, a portion of the top surface of the insulating layer106 is removed by the wet etch process. Therefore, the top corners ofthe conductive layer 108 can be made more rounded at the time of the dryetch process.

As described above, the invention has the following advantages.

Since the top corners of the conductive layer are made rounded, theconcentration of an electric field can be prevented.

Furthermore, the insulating layer is formed on the sides of the draincontact hole. Accordingly, a short problem can be prevented since adistance between the drain contact plug and the virtual power line issufficiently secured.

While the invention has been described in connection with practicalexemplary embodiments, the invention is not limited to the disclosedembodiments but, to the contrary, is intended to cover variousmodifications and equivalent arrangements included within the spirit andscope of the appended claims.

1. A method of manufacturing a semiconductor device, comprising thesteps of: forming an insulating layer over a semiconductor substrate;etching the insulating layer to expose the semiconductor substrate toform a contact hole having sides; forming an insulating layer on thesides of the contact hole; forming a conductive layer within the contacthole to form a contact plug; recessing a portion of a top surface of theinsulating layer; and etching a portion of upper portions of theconductive layer.
 2. The method of claim 1, comprising forming theinsulating layer using a nitride layer by a chemical vapor deposition(CVD) or atomic layer deposition (ALD) method.
 3. The method of claim 1,comprising forming the insulating layer to a thickness of 30 Å to 100 Å.4. The method of claim 1, comprising recessing the portion of a topsurface of the insulating layer employing a wet etch process.
 5. Themethod of claim 4, comprising: employing a H₃PO₄ solution in the wetetch process, and removing the insulating layer to a thickness of about50 Å to 100 Å.
 6. The method of claim 1, comprising etching the portionof the conductive layer employing a dry etch process using microwaveequipment or equipment in which a inductively coupled plasma (ICP)source is mounted.
 7. The method of claim 6, comprising performing thedry etch process using a mixed gas of SF₆ and Cl₂.
 8. The method ofclaim 7, wherein the mixed gas further comprises oxygen (O₂) gas.
 9. Themethod of claim 8, wherein the O₂ gas present in the mixed gas of SF₆and Cl₂ comprises about 5% to 10% of the total amount of the mixed gas.10. The method of claim 1, comprising performing step of etching theportion of the conductive layer using a hot SC-1 solution.
 11. Themethod of claim 1, comprising rounding top corners of the conductivelayer by the etch process.
 12. The method of claim 1, comprising etchingthe conductive layer to a thickness of 100 Å to 300 Å by the etchprocess.